(1) Field of the Invention
The invention relates to a trimming fuse circuit, and more particularly, to a circuit.
(2) Description of the Prior Art
Recently, with advance of photolithography technology and etching technology in semiconductor industry, the integrity density of single chip is almost three orders of magnitude than ten years ago. In achievement of such a highly integrated circuit, the advance of semiconductor processes make a great contribution that is second to none, and memory cell repair concept as well as trimming fuse circuit also make a great contribution. During each of semiconductor process, dies on wafer must be precisely processed and precisely controlled, which is a high technology. But even in deep sub-micron era, and even in nanometer era, active elements like MOS, bipolar transistors etc, and passive elements, like resistors, capacitors etc, have some mismatches, which cause yield losses. The one reason is that when elements are miniature, the control of doping impurity concentration is very sensitive to doping and anneal condition.
Therefore, in order to increase yield, adjusting the resistance of the circuit by using a trimming fuse circuit is important while the electrical performance of die is lower than expected but within a tolerable condition after testing. Generally, the trimming fuse circuit that includes a plurality of fuses, a few control signals, and several resistors that are connected in series, is to adjust an optimum or a desired current path. Once an electrical performance result is satisfied after testing, then the desired current path is saved, and the redundant fuses are burnt-out by high current or by laser, which are guided by pre-determined control signals.
Especially, the battery protection ICs is found to require reference voltages with high accuracy (+/−0.5%). It's very difficult to get reference voltage with high accuracy with high yield rate due to process deviation during IC fabrication. One of the methods to do this adjustment and to reduce the number of fuses the binary search approach is usually used.
Regarding the trimming circuit in the prior art, please refer to FIG. 1, presenting the simplified circuit of prior art. In FIG. 1, the circuit is composed of fuses F1, F2, F4, and F8, and several resistors. All the resistors are with the same resistance R permuted by forms of in series and parallel to form 16 ways of combination. The fuses F1, F2, F4, and F8 are interposed in between the nodes GND-A, A-B, B-C, and C-D. Between the nodes GND-A, four resistors are in parallel, and thus if the fuse F1 is burned, the resistance of the output terminal OUT will be increased by ¼ R. Between the nodes A-B, two resistors are in parallel, and thus if the fuse F2 is burned, the resistance of the output terminal OUT will be increased by ½ R. Between the nodes B-C, single resistor is placed, and thus if the fuse F4 is burned, the resistance of the output terminal OUT will be increased by R. Between the nodes C-D, two resistors are in series, and thus if the fuse F8 is burned, the resistance of the output terminal OUT will be increased by 2R.
Accordingly, as the fuses F1, F2, F4, and F8 shorts, it will correspond to 1, 2, 4, and 8 unit resistors, respectively. Each unit resistors defines 1 trimming step. Using a big current through a fuse or using laser, or using other methods to burn the fuse(s) can thus achieve the aims of adjusting the reference voltage. By this approach, the designed reference voltage is aimed at the value lower than the target value and then is adjusted.
Worth to note the trimming steps are always positive. The possible permutation of trimming steps and the corresponding combinations of the fuses burned are shown in table 1.
TABLE 1BurningF1F2F1,F4F1,F2,F1,F8F1,F2,F1,F4,F1,F2,F1,FusesF2F4F4F2,F8F8F2,F8F2,F4,F2,F4F8F8F8F4,F8Trimming+1+2+3+4+5+6+7+8+9+10+11+12+13+14+15Steps
Accordingly, the circuit shown in FIG. 1 provides only one direction trimming procedure, i.e., the trimming steps are always positive or only negative, as is shown in the Table 1. The relation of numbers of trimming steps with the fuses is like a binary code. That is the F1, F2, F4, and F8, respectively, as the lowest bit, second bit, third bit and the highest bit. For instance, the 11 trimming steps are correspondent to burning of F1, F2, and F8. total number of trimming steps=1+2+8.
Consequently, all fuses may need to be burned to meet the spec. however, the burning fuse procedure doesn't have 100% yield. It may sometimes damages internal circuit Besides, fuse burning procedures increase chip testing time.
In really, every adjusting parameter, for example, the battery protection IC the Over-Charge threshold voltage has however a minimum and maximum spec value (for example, 4.3V+/−25 mV), And modern IC fabrication processes have less variations than previous one. So, if our designed reference voltage is aimed at the typical spec value, we can avoid some burning of fuses